1. Field of the Invention
The present invention concerns a semiconductor device and a manufacturing method thereof. The present invention particularly relates to a semiconductor device having a trench gate structure and a manufacturing method thereof.
2. Description of Related Art
A semiconductor device having a “trench gate structure” in which a gate electrode is buried in a trench has been known. For example, Patent Document (Japanese Patent Application Laid-Open No. 2004-31385) discloses a vertical MOSFET (Vertical-type Metal Oxide Silicon Field-Effect Transistor) having a trench gate structure.
More specifically, Patent Document describes a technique for decreasing the gate resistance of a vertical MOSFET. The vertical MOSFET has a trench gate structure formed in a stripe shape to a semiconductor substrate in an actual operation region. Further, a lattice-like gate lead electrode in connection with the trench gate structure is provided on the actual operation region. Since the cross sectional area that can be utilized as a gate electrode is increased, the gate resistance is decreased.
FIG. 1 shows a cross sectional structure of a vertical MOSFET described in Patent Document. An N− type epitaxial layer 102 that functions as a drain region is formed over an N+ type semiconductor substrate 101. Further, a P type channel layer 120 is formed over the N− type epitaxial layer 102. Further, an N+ type source region 125 is formed to the surface of the P type channel layer 120. Plural trenches 110 are formed in a stripe shape to a semiconductor layer containing the epitaxial layer 102, the channel layer 120, and the source region 125. Each trench 110 is formed so as to reach the epitaxial layer 102 passing through the source region 125 and the channel layer 120.
A gate electrode 150 is formed by way of a gate oxide film 130 to the surface of each of the trenches 110. The gate electrode 150 has a buried portion 150a formed in the trench 110. That is, the vertical MOSFET shown in FIG. 1 has a trench gate structure. Further, the gate electrode 150 has a protruding portion 150b that protrudes from the trench 110 and a bridge portion (not illustrated) that connects protruding portions 150b adjacent with each other. Protruding portions 150 and bridge portions constitute a lattice-like gate lead electrode. It is to be noted that, as shown in FIG. 1, the protruding portion 150b extends in an eave shape from the opening of the trench 110 and has a width larger than that of the trench 110 (buried portion 150a). The wide protruding portion 150b also constitutes to the decrease of the gate resistance.
The surface of the protruding portion 150b of the gate electrode 150 is covered with an interlayer insulating film 160. Further, a contact hole 165 is formed so as to penetrate the interlayer insulating film 160 between the adjacent gate electrodes 150 and the source region 125. A P+ type body contact region 128 is formed to the channel layer 120 below the contact hole 165. Then, a source electrode 170 is formed so as to be in connection with the body contact region 128 and the source region 125.
FIG. 2A to FIG. 2E are cross sectional views showing manufacturing steps of the structure shown in FIG. 1. At first, as shown in FIG. 2A, an N− type epitaxial layer 102 that functions as a drain region is formed above the N+ type semiconductor substrate 101. Successively, a P type channel layer 120 is formed in the epitaxial layer 102 through an ion implantation and thermal diffusion treatment. Further, stripe-like trenches 110 are formed through anisotropic dry etching by using a mask having a predetermined pattern. Each trench 110 is formed so as to reach the epitaxial layer 102 penetrating the channel layer 120. Then, a thermal oxidation treatment is carried out to form a gate oxide film 130 over the entire surface.
Then, as shown in FIG. 2B, a non-doped polysilicon layer 140 is deposited over the entire surface. Further, for increasing the conductivity, phosphorus at a high concentration is introduced into the polysilicon layer 140. Then, as shown in FIG. 2C, an NSG (Non-doped Silicate Glass) film 145 having a predetermined pattern is formed as a mask which is used for patterning an upper gate electrode 150 (protruding portion 150b, bridge portion). Then, the polysilicon layer 140 is etched by using the NSG film 145 as a mask. As a result, as shown in FIG. 2D, the gate electrode 150 (protruding portion 150b, bridge portion) having a predetermined pattern is formed. In this case, it is to be noted that the protruding portion 150b is formed to a width larger than that of the trench 110 (buried portion 150a) for decreasing the gate resistance.
Then, as shown in FIG. 2E, an N+ type impurity is ion implanted for forming an N+ type source type region 125. Then, after ion implantation, a thermal diffusion treatment at a high temperature is carried out. As a result, an N+ type source region 125 is formed to the surface of the channel layer 120 between adjacent trenches 110. Then, an interlayer insulating film 160, a contact hole 165, a body contact region 128, a source electrode 170, etc. are formed.